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ds96wrl0601 p r e l i m i n a r y 2-1 2 p reliminary p roduct s pecification Z87010/z87l10 2 a udio e ncoder /d ecoders features hardware n 16-bit dsp processor n 3.0v to 3.6v; -20 to +70 c, z87l10 4.5v to 5.5v, -20 to +70 c, Z87010 n static architecture n 512 word on-chip ram n modified harvard architecture n direct interface to z87000 frequency hopping spreader/despreader n direct interface to 8-bit m -law telephone codec n i/o bus (16-bit tristable data, 3-bit address) n wait state generator n two external interrupts n four separate i/o pins (2 input, 2 output) software n full duplex 32 kbps adpcm encoding/decoding n single tone and dtmf signal generation n sidetone, volume control, mute functions n large phone number memory (21 numbers of 23 digits each) n master-slave protocol interface to z87000 spreader/- despreader general description the Z87010/z87l10 is a second generation cmos digital signal processor (dsp) that has been rom-coded by zilog to provide full-duplex 32 kbps, adaptive delta pulse code modulation (adpcm) speech coding/decoding (co- dec), and interface to the z87000/z87l00 spread spec- trum cordless telephone controller. together the z87000/z87l00 and Z87010/z87l10 devices support the implementation of a 900 mhz frequency-hopping spread spectrum cordless telephone in conformance with united states fcc regulations for unlicensed operation. the Z87010 and z87l10 are distinct 5v and 3.3v versions of the adpcm audio encoder/decoder. for the sake of brevity, all subsequent references to the Z87010 in this document also are applicable to the z87l10, unless spe- cifically noted. the Z87010? single cycle instruction execution and har- vard bus structure promote efficient algorithm execution. the processor contains a 4k word program rom and 512 word data ram. six dual operand fetching. three vectored interrupts are complemented by a six level stack. the co- dec interface enables high-speed transfer rate to accom- modate digital audio and voice data. a dedicated counter/timer provides the necessary timing signals for the codec interface. an additional 13-bit timer is dedicat- ed for general-purpose use. the Z87010? circuitry is optimized to accommodate intri- cate signal processing algorithms and is used here for speech compression/decompression, generation of dtmf tones and other cordless telephone functions. dedicated hardware allows direct interface to a variety of codec device rom (kbyte) i/o lines package information Z87010 4 16 44-pin plcc 44-pin qfp z87l10 4 16 44-pin qfp
Z87010/z87l10 audio encoder/decoders zilog 2-2 p r e l i m i n a r y ds96wrl0601 general description (continued) ics. as configured by the zilog-provided embedded soft- ware for digital cordless phones, the Z87010 supports a low-cost 8-bit m -law telephone codec. the Z87010 is to be used with the z87000 and operates at 16.384 mhz, pro- viding 16 mips of processing power needed for the cord- less telephone application. notes: all signals with a preceding front slash, ?? are active low, e.g., b//w (word is active low); /b/w (byte is active low, only). power connections follow conventional descriptions be- low: figure 1. Z87010 functional block diagram 16-bit i/o interface /rdye er//w /ei ea0-2 ext 0-15 256 word ram0 256 word ram1 dsp core wait state generator 13-bit timer codec interface 4k words program rom rxd txd sclk fs0 fs1 uo0-1 ui0-1 /reset /int0-2 power vdd vss dual connection circuit device power v cc v dd ground gnd v ss
Z87010/z87l10 zilog audio encoder/decoders ds96wrl0601 p r e l i m i n a r y 2-3 2 pin description figure 2. 44-pin plcc pin assignments Z87010 7 17 vss ext0 ext1 ext2 vss rxd ext12 ext13 ext14 vss ext15 ea0 /reset wait rd//wr vdd sclk ui0 ui1 /int1 /int2 ext11 ext3 ext4 vss ext5 ext6 ext7 txd ext8 ext9 vss ext10 fs1 uo1 uo0 /into fso halt clk /ds vdd ea2 ea1 1 28 18 40 39 29 6
Z87010/z87l10 audio encoder/decoders zilog 2-4 p r e l i m i n a r y ds96wrl0601 pin description (continued) table 1. 44-pin plcc pin identi?ation no. symbol function direction 1 halt stop execution input 2 fs0 codec0 frame sync input/output* 3 /int0 interrupt input 4-5 uo0-uo1 user output output 6 fs1 codec1 frame sync input/output* 7,11,16,20,27 v ss ground 8-10 ext0-ext2 external data bus input/output 12 rxd serial input from codecs input 13-15 ext12-ext14 external data bus input/output 17 ext15 external data bus input/output 18-19 ext3-ext4 external data bus input/output 21-23 ext5-ext7 external data bus input/output 24 txd serial output to codecs output 25-26 ext8-ext9 external data bus input/output 28-29 ext10-ext11 external data bus input/output 30 /int2 interrupt input 31 /int1 interrupt input 32 ui1 user input input 33 ui0 user input input 34 sclk codec serial clock input/output* 35,42 v dd power supply input 36 rd//wr rd /wr strobe for ext bus output 37 wait wait state input 38 /reset reset input 39-41 ea0-ea2 external address bus output 43 /ds data strobe for external bus output 44 clk clock input note: *defined input or output by interface mode selection
Z87010/z87l10 zilog audio encoder/decoders ds96wrl0601 p r e l i m i n a r y 2-5 2 figure 3. 44-pin qfp pin assignments 34 44 1 23 33 Z87010 11 22 12 ext3 ext4 vss ext5 ext6 ext7 txd ext8 ext9 vss ext10 fs1 uo1 uo0 /int0 fso halt ck /ei vdd ea2 ea1 ea0 /res /rdye er//w vdd sclk ui0 ui1 /int1 /int2 ext11 vss ext0 ext1 ext2 vss rxd ext12 ext13 ext14 vss ext15
Z87010/z87l10 audio encoder/decoders zilog 2-6 p r e l i m i n a r y ds96wrl0601 pin description (continued) table 2. 44-pin qfp pin identi?ation no. symbol function direction 1-2 ext3-ext4 external data bus input/output 3,10 v ss ground 4-6 ext5-ext7 external data bus input/output 7 txd serial output to codecs output 8-9 ext8-ext9 external data bus input/output 11-12 ext10-ext11 external data bus input/output 13 /int2 interrupt input 14 /int1 interrupt input 15 ui1 user input input 16 ui0 user input input 17 sclk codec serial clock input/output* 18,25 v dd power supply input 19 er//w r/w for external bus output 20 /rdye data ready input 21 /res reset input 22-24 ea0-ea2 external address bus output 26 /ei data strobe for external bus output 27 ck clock input 28 halt stop execution input 29 fs0 codec0 frame sync input/output* 30 /int0 interrupt input 31-32 u00-u01 user output 33 fs1 codec1 frame sync input/output* 34 v ss ground input 35-37 ext0-ext2 external data bus input/output 38 v ss ground input 39 rxd serial input to codec input 40-42 ext12-ext14 external data bus input/output 43 v ss ground input 44 ext15 external data bus input/output note: *input or output is defined by interface mode selection.
Z87010/z87l10 zilog audio encoder/decoders ds96wrl0601 p r e l i m i n a r y 2-7 2 absolute maximum rating stresses greater than those listed under absolute maxi- mum ratings may cause permanent damage to the de- vice. this is a stress rating only; operation of the device at any condition above those indicated in the operational sec- tions of these specifications is not implied. exposure to ab- solute maximum rating conditions for extended period may affect device reliability. standard test conditions the characteristics listed below apply for standard test conditions as noted. all voltages are referenced to ground. positive current flows into the referenced pin (figure 4). standard test conditions are as follows: 3.0v v dd 3.6v (z87l10) 4.5v v dd 5.5v (Z87010) v ss = 0v t a = -20 to +70 c symbol description min. max. units v dd supply voltage -0.3 +7.0 v t stg storage temp -65 c +150 cc t a oper. ambient temp -25 +70 c note: *voltage on all pins with respect to gnd. figure 4. test load diagram output under test iol ioh threshold voltage 50pf
Z87010/z87l10 audio encoder/decoders zilog 2-8 p r e l i m i n a r y ds96wrl0601 dc electrical characteristics v dd = 4.5v to 5.5v (Z87010) v dd = 3.0v to 3.6v (z87l10) t a =-20 c to +70 c symbol parameter condition min max units i dd supply current v dd =5.5v fclock=16.384 mhz 40 ma i dc dc power consumption v dd =5.5v 0.2 ma v ih input high level 2.7 v v il input low level 0.8 v i l input leakage 10 m a v oh output high voltage i oh =-100 m av dd -0.2 v v ol output low voltage i ol =2.0 ma 0.5 v (1) i fl output floating leakage current 10 m a note: 5. the following specifications are pin specific: ea0-2 has i ol = 5 ma @ 0.5v 6. i oh = 1 ma @ 3.3v t a =-20 c to +70 c symbol parameter condition min max units i dd supply current v dd =3.6v fclock=16.384 mhz 25 ma i dc dc power consumption v dd =3.6v 0.2 ma v ih input high level .7v dd v dd +.3 v v il input low level vss-.3 .1v dd v i l input leakage 10 m a v oh output high voltage i oh =-50 m av dd -0.2 v v ol output low voltage i ol =1.0 ma 0.5 v (1) i fl output floating leakage current 10 m a note: 7. the following specifications are pin specific: ea0-2 has i ol = 5 ma @ 0.5v 8. i oh = 1 ma @ 3.3v
Z87010/z87l10 zilog audio encoder/decoders ds96wrl0601 p r e l i m i n a r y 2-9 2 ac electrical characteristics ) t a = -20 c to +70 c symbol parameter min (ns) max (ns) tcy clock cycle time 50 pww clock pulse width 23 tr clock rise time 2 tf clock fall time 2 tead ea, er//w delay from ck 5 28 txvd ext data output valid from ck 5 33 txwh ext data output hold from ck 3 25 txrs ext data input setup time 10 txrh ext data input hold from ck 10 25 tiedr /ei delay time from ck 3 15 tiedf 0 15 rdys ready setup time 8 rdyh ready hold time 5 tins int. setup time to clk fall 3 _ tinl int. low pulse width 10 ths halt setup time to clk rise 3 thh halt hold time to clk rise 10
Z87010/z87l10 audio encoder/decoders zilog 2-10 p r e l i m i n a r y ds96wrl0601 ac timing diagrams figure 5. write to external device timing ck /ei er//w ext (15:0) ea (2:0) valid address out valid data out rdys /rdye ext bus: output tead tcy pww txwh txvd tiedf tiedr tead tead rdyh
Z87010/z87l10 zilog audio encoder/decoders ds96wrl0601 p r e l i m i n a r y 2-11 2 figure 6. read from external device timing ck /ei er//w ext (15:0) ea (2:0) valid address out valid data in /rdye ext bus: input tead tcy pww txrh txrs tiedf tied tead rdys rdyh
Z87010/z87l10 audio encoder/decoders zilog 2-12 p r e l i m i n a r y ds96wrl0601 ac timing diagrams (continued) figure 7. interrupt/halt timing table 3. codec interface-ac timing internal sclk min max sdcr sclk down from clk rise 15 sucr sclk up from clk rise 15 fdcr fs0, fs1 down from sclk rise 6 fucr fs0, fs1 up from sclk rise 6 tdsr txd down from sclk rise 7 tusr txd up from sclk rise 7 rsu rxd setup time in respect to sclk fall 7 rh rxd hold time in respect to sclk fall 0 fdcr fs0,fs1 down from sclk rise 13 fucr fs0, fs1 up from sclk rise 13 tdsr txd down from sclk rise 12 tusr txd up from sclk rise 12 rsu rxd setup time in respect to sclk fall 1 rh rxd hold time in respect to sclk fall 6 ck interrupt halt ths thh tins tinl
Z87010/z87l10 zilog audio encoder/decoders ds96wrl0601 p r e l i m i n a r y 2-13 2 figure 8. codec interface timing clock sclk fs0, 1 txd rxd sdcr tcy fdcr tusr tdsr rsv rh susr fucr
Z87010/z87l10 audio encoder/decoders zilog 2-14 p r e l i m i n a r y ds96wrl0601 pin functions ck clock (input). this pin controls the external clock. ext15-ext0 external data bus (input/output). data bus for user-defined outside registers. the pins are normally tri-stated, except when the outside registers are specified as destination registers in the instructions. all the control signals exist to allow a read or a write through this bus. the bus is used for z87000 interface. er//w external bus direction (output). data direction sig- nal for ext-bus. data is available from the cpu on ext15-ext0 when this signal is low. ext-bus is in input mode (high-impedance) when this signal is high. ea2-ea0 external address (output). user-defined register address output (latched). one of eight user-defined exter- nal registers is selected by the processor with these ad- dresses are part of the processor memory map, the pro- cessor is simply executing internal reads and writes. external addresses ext4-ext7 are used internally by the processor if the codec interface and 13-bit timer are en- abled. /ei enable input (output). read/write timing signal for ext-bus. user strobe is for triggering external peripheral. data is read by the external peripheral on the rising edge of /ei. data is read by the processor on the rising edge of ck not /ei. halt halt state (input). stop execution control. the cpu continuously executes nops and the program counter re- mains at the same value when this pin is held high. this signal must be synchronized with ck. an interrupt request must be executed (enabled) to exit halt mode. after the interrupt service routine, the program continues from the instruction after the halt. /int2-/int0 three interrupts (input, active low). interrupt request 2-0. interrupts are generated on the rising edge of the input signal. interrupt vectors for the interrupt service routine starting address are stored in the program memory locations 0fffh for /int0, 0ffeh for /int1, and 0fffdh for /int2. priorities are: int2=lowest, int0=highest. int1 and int2 are shared with internal Z87010 peripher- als. int1 is dedicated to the codec interface if enabled. int2 services the 13-bit timer if enabled. in the Z87010 standard software configuration, int0 and int2 are not used; int1 is used by the codec interface. /res reset (input, active low). this pin controls the asyn- chronous reset signal. the /reset signal must be kept low for at least one clock cycle. the cpu pushes the con- tents of the program counter (pc) onto the stack and then fetches a new pc value from program memory address 0ffch after the reset signal is released. /rdye data ready (input). user-supplied data ready sig- nal for data to and from external data bus. this pin stretch- es the /ei and er//w lines and maintains data on the ad- dress bus and data bus. the ready signal is sampled from the rising clock only if ready is active. a single wait-state can be generated internally by setting the appropriate bits in the ext7-2 register. ui1-ui0 two input pins (input). general-purpose input pins. these input pins are directly tested by the conditional branch instructions: and are reflected in two bits of the sta- tus register (s10 and s11). these are asynchronous input signals that have no special clock synchronization require- ments. u01-u00 two output pins (push-pull output). general- purpose output pins. these pins reflect the value of two bits in the status register (s5 and s6). uo0 is dedicated to provide an interrupt signal to the z87000 controller. note: the user output pin values are the inverse of the status reg- ister content.
Z87010/z87l10 zilog audio encoder/decoders ds96wrl0601 p r e l i m i n a r y 2-15 2 functional description general functional partitioning of the Z87010 is shown in figure 1. the chip consists of the z89s00 static dsp core with 512 words of ram, 4k words of rom, a codec in- terface, a general-purpose timer and a wait state genera- tor. the dsp core is characterized by an efficient hardware ar- chitecture that allows fast arithmetic operations such as multiplication, addition, subtraction and multiply-accumu- late of two 16-bit operands. most instructions are executed in one clock cycle. the dsp core uses a ram memory of 512 16-bit words di- vided in two banks. program memory. the Z87010 has a 4k 16-bit words in- ternal rom including 4 words for interrupt and reset vec- tors. the rom is mapped at address 0000h to 0fffh. the reset vector is located at address 0ffch, interrupts int0 is at 0ffdh, interrupt int1 is at 0ffeh and interrupt int2 is at 0fffh. interrupts. the Z87010 has three positive edge-triggered interrupt inputs pins. however, int1 is dedicated to the codec interface and int2 is dedicated to the 13-bit timer if these peripherals are enabled. user inputs. the Z87010 has two inputs, ui0 and ui1, which may be used by jump and call instructions. the jump or call tests one of these pins and if appropriate, jumps to a new location. otherwise, the instruction be- haves like a nop. these inputs are also connected to the status register bits s10 and s11, which may be read by the appropriate instruction. user outputs. the status register bits s5 and s6 connect directly to uo0 and uo1 pins and may be written to by the appropriate instruction. note: the user output value is the opposite of the status register content. i/o bus. the Z87010 provides a 16-bit, cmos compatible i/o bus. i/o control pins provide convenient communica- tion capabilities with external peripherals. single cycle ac- cess is possible. for slower communications, an on-board hardware wait-state generator can be used to accommo- date timing conflicts. these latched output address pins (ea0-2) allow a maxi- mum of eight external peripherals. however up to four of these addresses (ext4-7) are used by internal peripherals if enabled. ext4 13-bit timer configuration register ext5 codec interface channel 0 data ext6 codec interface channel 1 data ext7 codec interface configuration register and wait state generator.
Z87010/z87l10 audio encoder/decoders zilog 2-16 p r e l i m i n a r y ds96wrl0601 codec interface the codec interface provides direct-connect capabilities for standard 8-bit pcm codecs with hardware m -law compression. internal registers ext5, ext6 and ext7 are used to program the codec mode. one serial clock and two frame sync control signals are provided, allowing for two bidirectional data channels. note: m -law expansion must be done in software. codec interface hardware the hardware for the codec interface uses six 16-bit registers, m -law compression logic and general-purpose logic to control transfers to the appropriate register. codec interface control signals sclk (serial clock) the serial clock provides a clock signal for operating the external codec. a 4-bit prescaler is used to determine the frequency of the output signal. sclk = (0.5* clk)/ps where: clk = system clock ps = 4-bit prescaler* note: an internal divide-by-two is performed before the clock signal is passed to the serial clock prescaler. * the prescaler is an up-counter. figure 9. codec interface block diagram m -law compression data bus 16 16 16 16 16 16 clkin txd ext5-2 clkin clkin clkin clkin ext5-1 ext6-1 ext6-2 control logic rxd ext7-1 ext7-2 16
Z87010/z87l10 zilog audio encoder/decoders ds96wrl0601 p r e l i m i n a r y 2-17 2 assuming an input clock of 16.384 mhz, sclk is pro- grammed by the Z87010 embedded software for 2.048 mhz. txd (serial output to codec) the txd line provides 8-bit data transfers. each bit is clocked out of the processor by the rising edge of the sclk, with the msb transmitted first. rxd (serial input from codec) the rxd line provides 8-bit data transfers. each bit is clocked into the processor by the falling edge of the sclk, with the msb received first. fs0, fs1 (frame sync) the frame sync is used for enabling data transfer/receive. the rising and falling edge of the frame sync encloses the serial data transmission. the Z87010 embedded software programs the frame sync signal to 8 khz. interrupt once the transmission of serial data is completed an inter- nal interrupt signal is initiated. a single-cycle low pulse provides an interrupt on int1. when this occurs, the pro- cessor will jump to the defined interrupt 1 vector location. codec interface timing figure 10 depicts a typical 8-bit serial data transfer using both of the codec interface channels. the transmitting data is clocked out on the rising edge of the sclk signal. an external codec clocks data in on the falling edge of the sclk signal. once the serial data is transmitted, an in- terrupt is given. the codec interface signals are not initi- ated if the codec interface is not enabled. the following modes are available for fsync and sclk signals: figure 10. codec interface timing (8-bit mode) /int1 fs1 sclk fs0 txd rxd sclk fsync internal internal external external external internal internal external
Z87010/z87l10 audio encoder/decoders zilog 2-18 p r e l i m i n a r y ds96wrl0601 codec interface (continued) the codec interface timing is independent of the proces- sor clock when external mode is chosen. this feature pro- vides the capability for an external device to control the transfer of data to the Z87010. the frame sync signal en- velopes the transmitted data (figure 10), therefore care must be taken to ensure proper sync signal timing. in the cordless phone system, the sclk is externally provided by the z87000 controller, while fsync is internally gener- ated. the transmit and receive lines are used for transfer of se- rial data to or from the codec interface. the codec in- terface performs both data transmit and receive simulta- neously. the fsync signals (fs0, fs1) when programmed for in- ternal mode, are generated by 9-bit counter with sclk as input clock. together with the sclk prescaler, this counter forms a 13-bit counter clocked by the system clock divided by two. the output of this counter can be used to clock the general-purpose 13-bit counter/timer, to form a 26-bit counter. codec control registers the codec interface is accessed through addresses ext5, ext6 and ext7. the data accesses are double- buffered registers: two registers (ext5-1 and ext5-2) are mapped on address ext5 and similarly ext6-1 and ext6-2 registers are mapped on address ext6. figure 11. codec interface data registers (channel 0) d15 d14 d13 d11 d10 d9 d8 d12 d7 d6 d5 d4 d3 d2 d1 d0 ext5-1 data bits 15-0 d15 d14 d13 d11 d10 d9 d8 d12 d7 d6 d5 d4 d3 d2 d1 d0 ext5-2 data bits 15-0 figure 12. codec interface data registers (channel 1) d15 d14 d13 d11 d10 d9 d8 d12 d7 d6 d5 d4 d3 d2 d1 d0 ext6-1 data bits 15-0 d15 d14 d13 d11 d10 d9 d8 d12 d7 d6 d5 d4 d3 d2 d1 d0 ext6-2 data bits 15-0
Z87010/z87l10 zilog audio encoder/decoders ds96wrl0601 p r e l i m i n a r y 2-19 2 figure 13. codec interface control register d7 d6 d5 d4 d3 d2 d1 d0 d15 d14 d13 d12 d11 d10 d9 d8 sclk prescaler (up-counter) ext7-1 sclk/fsync ratio prescaler (up-counter) codec mode 01 reserved 10 reserved 11 reserved fsync 0 external source* 1 internal source codec 0 disable/enable 0 = disable* 1 = enable note: the timer is an up-counter. example: ext7-1 = #%x00d osc = 12.288 mhz, sclk = 2.048 mhz, fsync = 8 khz ext7-1 = #%x80f osc = 12.288 mhz, sclk = 6.144 mhz, fsync = 48 khz ext7-1 = #%xffx no interrupt ext7-1 = #%x000 max interrupt period (667 m s for osc = 12.288 mhz) * default figure 14. wait/state/codec interface control register d7 d6 d5 d4 d3 d2 d1 d0 d15 d14 d13 d12 d11 d10 d9 d8 ext7-2 wait state ext0 wait state ext1 wait state ext2 wait state ext3 wait state ext4 wait state ext5 wait state ext6 sclk 0 external source* 1 internal source codec 1 disable/enable 0 = disable* 1 = enable nws - no wait states ws - one wait states 00 no wait states (nws) 01 read (nws), write (ws) 10 read (ws), write (nws) 11 read (ws), write (ws) *default
Z87010/z87l10 audio encoder/decoders zilog 2-20 p r e l i m i n a r y ds96wrl0601 codec interface (continued) the codec interface control register (ext7-1) is shown on figure 13. setting of the codec mode, fsync mode and codec 0 enable/disable is done through this register. a second control register (ext7-2) also mapped on ad- dress ext7 control the codec 1, sclk source and wait state generator (see figure 9). the ?peration?section de- scribes how to access the various register. wait-state generator an internal wait state generator is provided to accommo- date slow external peripherals. one wait-state can be au- tomatically inserted by the Z87010 in any ext bus access. read and/or write cycles can be independently lengthened for each register, by setting register ext7-2 accordingly. see figure 9 for detailed description of ext7-2. the Z87010 software uses one wait state on all external register accesses. for additional wait states, a dedicate pin (/rdye) can be held high. the /rdye pin is monitored only during execu- tion of a read or write instruction to external peripherals. general-purpose counter timer a 13-bit counter/timer is available for general-purpose use. when the counter counts down to the zero state, an inter- rupt is received on int2. if the counter is disabled, ext4 can be used as a general-purpose address. the counting operation of the counter can be disabled by resetting bit 14. by selecting the clock source to the codec counter output (fsync), one can extend the counter to a total of 26 bits. note: placing zeroes into the count value register does not generate an interrupt. therefore it is possible to have a single-pass option by loading the counter with zero after the start of count. the counter is defaulted to the enable state. if the system designer does not choose to use the timer, the counter can be disabled. once disabled, the designer cannot enable the counter unless a reset of the processor is performed. example: ld ext, #%c0008 1100 0000 0000 1000 ; enable counter ; enable counting ; clock source = osc/2 ; count value = 1000=8 ; interrupt will occur every 16 clock cycles figure 15. timer register d7 d6 d5 d4 d3 d2 d1 d0 d15 d14 d13 d12 d11 d10 d9 d8 ext4 count value (down-counter) clock source count operation counter 0 oscillator/2* 1 codec counter output 0 = disable* 1 = enable 0 = disable 1 = enable* * default state
Z87010/z87l10 zilog audio encoder/decoders ds96wrl0601 p r e l i m i n a r y 2-21 2 operation disabling peripherals disabling a properly (codec interface, counter) provides a general-purpose use of the ext address pertaining to the specific peripheral. if the peripheral is not disabled, the ext control signals and ext data are still provided but transfer of data on the ext pins is not available (since in- ternal transfers are being processes on the internal bus). care must be taken to ensure that control of the ext bus does not provide bus conflicts. accessing the codec interface registers ext5, ext6 and ext7 host double buffered registers. external serial codec data is transferred from pin rxd to the Z87010 codec interface registers ext5-2. at the same time, the data present in ext5-2 is serially trans- ferred to the external codec through pin txd. writing a new data word to ext5 loads that data word to ext5-2 and transfers the current contents of ext5-2 to ext5-1. reading data from ext5 reads the contents of ext5-1. core must be taken to ensure that ext5 is not written to while the serial codec transfer is taking place. this is achieved by only writing to ext5 after the codec interrupt. this also transfers the codec value to ext5-1 which can be read in software. the correct succession of operations is thus 1. wait for interrupt 2. write to ext5 3. read from ext5 the same discussion applies for ext6. a similar hardware architecture is used for ext7. writing to ext7 loads the register ext7-2 and transfers the previ- ous contents of ext7-2 to ext7-1. reading from ext7 re- turns the contents of ext7-1. in order to load both registers, two successive load opera- tions to ext7 are required: first with the contents of ext7- 1 then with the contents of ext7-2. (see figure 16). figure 16. ext7 register con?uration internal 16-bit bus wait-state register 16 ext7-1 ext7-2 16 codec timer register ext7-1 ext7-2

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